SH7032 Datasheet, PDF (120/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 User Break Controller (UBC)
6.5 Notes
6.5.1 On-Chip Memory Instruction Fetch
Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on
the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
6.5.2 Instruction Fetch at Branches
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are
fetched and executed as follows:
1. Conditional branch instruction, branch taken: BT, BF
Instruction fetch cycles: Conditional branch fetch → Next-instruction overrun fetch → Next-
but-one-instruction overrun fetch → Branch destination fetch
Instruction execution: Conditional branch instruction execution → Branch destination
instruction execution
2. TRAPA instruction, branch taken: TRAPA
Instruction fetch cycles: TRAPA instruction fetch → Next-instruction overrun fetch → Next-
but-one-instruction overrun fetch → Branch destination fetch
Instruction execution: TRAPA instruction execution → Branch destination instruction
execution
When a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination will be fetched after the next instruction or the one after that does an overrun fetch.
When the next instruction or the one after that is set as a break condition, a branch will result in
the generation of a user break interrupt at the next instruction or the instruction after that, neither
of which instructions will be executed.
Rev. 7.00 Jan 31, 2006 page 94 of 658
REJ09B0272-0700