SH7032 Datasheet, PDF (271/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.2.9 Timer Control Register (TCR)
The ITU has five 8-bit timer control registers (TCR), one for each channel.
TCR is an 8-bit read/write register that selects the timer counter clock, the edges of the external
clock source, and the counter clear source. TCR is initialized to H'80 or H'00 by a reset and in
standby mode.
Table 10.7 Timer Control Register (TCR)
Channel
0
1
2
3
4
Abbrevi-
ation
TCR0
TCR1
TCR2
TCR3
TCR4
Function
TCR controls the TCNTs. The TCRs have the same functions on all channels.
When channel 2 is set for phase counting mode, setting the CKEG1, CKEG2,
and TPSC2–TPSC0 bits will have no effect.
Bit
Initial value
Read/Write
Note: * Undefined
7
6
5
4
3
2
1
0
— CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
*
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—Reserved: Bit 7 is read as undefined. The write value should be 0 or 1.
Rev. 7.00 Jan 31, 2006 page 245 of 658
REJ09B0272-0700