SH7032 Datasheet, PDF (179/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
8.5.5 DRAM Burst Mode
In addition to the normal mode of DRAM access, in which row addresses are output at every
access and data then accessed (full access), the DRAM also has a high-speed page mode for use
when continuously accessing the same row. The high speed page mode enables fast access of data
simply by changing the column address after the row address is output (burst mode). Select
between full access and burst operation by setting the burst enable bit (BE) in DCR. When the BE
bit is set to 1, burst operation is performed when the row address matches the previous DRAM
access row address. Figure 8.22 shows a comparison between full access and burst operation.
RAS
CAS
A21–A0
AD15–
AD0
Column address 1
Row address 1
Row address 2
Data 1
(a) Full access (read cycle)
Column
address 2
Data 2
RAS
CAS
A21–A0
AD15–
AD0
Column Column Column Column
address 1 address 2 address 3 address 4
Row address 1
Data 1 Data 2 Data 3
(b) Burst operation (read cycle)
Data 4
Figure 8.22 Full Access and Burst Operation
Short pitch high-speed page mode or long pitch high-speed page mode burst transfers can be
selected independently for DRAM read/write cycles even when burst operation is selected by
using the bits corresponding to area 1 in WCR1 and WCR2 (RW1, WW1, DRW1, DWW1). RAS
down mode or RAS up mode can be selected by setting the RAS down bit (RASD) in DCR when
there is an access outside the DRAM space during burst operation.
Rev. 7.00 Jan 31, 2006 page 153 of 658
REJ09B0272-0700