SH7032 Datasheet, PDF (240/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
T1 T2 T3 T4
CK
T1 T2 T3 T4
DREQ
Bus cycle
CPU CPU CPU
DMAC(R)
DMAC
(W)
CPU
DMAC (R)
DMAC
(W)
CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
Figure 9.22 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = Address/Data
Multiplex I/O Bus Cycle)
• DREQ pin sampling timing in burst mode
In burst mode, the sampling timing differs depending on whether DREQ is detected by edge or
level.
When DREQ input is being detected by edge, once the falling edge of the DREQ signal is
detected, the DMA transfer continues until the transfer end conditions are satisfied, regardless
of the status of the DREQ pin. No sampling happens during this time. After the transfer ends,
sampling occurs every state until the TE bit of CHCR is cleared.
When DREQ input is being detected by level, once the DREQ input is detected, subsequent
sampling is performed at the end of every CPU or DMAC bus cycle in single address mode. In
dual address mode, subsequent sampling is performed at the start of every DMAC read cycle.
In both single address mode and dual address mode, if no DREQ input is detected at this time,
subsequent sampling occurs at every state.
Figures 9.23 and 9.24 show the DREQ pin sampling timing in burst mode when DREQ input is
detected by low level.
Rev. 7.00 Jan 31, 2006 page 214 of 658
REJ09B0272-0700