SH7032 Datasheet, PDF (195/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
8.10 Bus Arbitration
The SuperH microcomputer can release the bus to external devices when they request the bus. It
has two internal bus masters, the CPU and the DMAC. Priorities for releasing the bus for these
two are as follows.
Bus request from external device > refresh > DMAC > CPU
Thus, an external device has priority when it generates a bus request, even when the DMAC is
carrying out a burst transfer.
Note that when a refresh request is generated while the bus is released to an external device,
BACK goes high and the bus can be acquired to perform refreshing upon receipt of a BREQ =
high response from the external device. Input all bus requests from external devices to the BREQ
pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 8.35
illustrates the bus release procedure.
SuperH
BREQ received
BREQ = low
Strobe pin:
High-level output
Address, data, strobe pin: _{BACK = low}
High impedance
Bus release response
External device
Bus request
BACK acknowledge
Bus acquisition
Bus released
Figure 8.35 Bus Release Procedure
Rev. 7.00 Jan 31, 2006 page 169 of 658
REJ09B0272-0700