SH7032 Datasheet, PDF (11/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
20.1.3 AC
486
Characteristics
(3) Bus Timing
Figure 20.9 Basic
Bus Cycle: Two-
State Access
Figure 20.12 (b) 490
DRAM Bus Cycle
(Short-Pitch, High-
Speed Page Mode:
Write)
Revision (See Manual for Details)
Note amended
Note 2. For tACC2, use tcyc × (n + 2) – 30 instead of tcyc × (n + 2) –
tAD (or tCSD1) – tRDS.
Figure amended
WRH, WRL,
WR (Write)
t_WSD3
t_WSD4
20.1.3 AC
502
Characteristics
(3) Bus Timing
Figure 20.22 Basic
Bus Cycle: Two-
State Access
Figure 20.25 (b) 506
DRAM Bus Cycle
(Short-Pitch, High-
Speed Page Mode:
Write)
AD15–AD0
DPH, DPL
(Write)
t_WDD2
t_WDH
t_WPDD2
t_WPDH
DPH, DPL
(Write)
Note amended
Note 2. For tACC2, use tcyc × (n + 2) – 44 instead of tcyc × (n + 2) –
tAD (or tCSD1) – tRDS.
Figure amended
WRH, WRL,
WR (Write)
t_WSD3
t_WSD4
AD15–AD0
DPH, DPL
(Write)
DPH, DPL
(Write)
t_WDD2
t_WDH
t_WPDD2
t_WPDH
Rev. 7.00 Jan 31, 2006 page xi of xxvi