SH7032 Datasheet, PDF (310/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.4.8 Buffer Mode
In buffer mode, the buffer operation functions differ depending on whether the general registers
are set to output compare or input capture, reset-synchronized PWM mode, or complementary
PWM mode. Buffer mode is a function of channels 3 and 4 only. Buffer operations set this way
function as follows.
GR is an Output Compare Register: The value of the buffer register of a channel is transferred
to GR when a compare match occurs in the channel. This is illustrated in figure 10.45.
Compare match signal
BR
GR
Comparator
TCNT
Figure 10.45 Compare Match Buffer Operation
GR is an Input Capture Register: TCNT values are transferred to GR when input capture occurs
and the value previously stored in GR is transferred to BR. This operation is illustrated in figure
10.46.
Input capture signal
BR
GR
TCNT
Figure 10.46 Input Capture Buffer Operation
Complementary PWM Mode: When the count direction of TCNT3 and TCNT4 changes, the BR
value is transferred to GR. The following timing is employed for this transfer:
• When there is a TCNT3/GRA3 compare-match
• When there is a TCNT4 underflows
Rev. 7.00 Jan 31, 2006 page 284 of 658
REJ09B0272-0700