SH7032 Datasheet, PDF (275/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bits 2–0—I/O Control A2–A0 (IOA2–IOA0): IOA2–IOA0 select the GRB function.
Bit 2: Bit 1: Bit 0: GRA
IOA2 IOA1 IOA0 Function
0
0
0
GRA is an Compare match with pin output disabled (Initial value)
1
1
0
output
compare
register
0 output at GRA compare match*¹
1 output at GRA compare match*¹
1
Output toggles at GRA compare match (1 output for
channel 2 only)*¹ *²
1
0
0
GRA is an GRA captures rising edge of input
1
input capture
register
GRA captures falling edge of input
1
0
GRA captures both edges of input
1
Notes: 1. After reset, the value output is 0 until the first compare match occurs.
2. Channel 2 has no compare-match driven toggle output function. If it is set for toggle, 1
is automatically selected as the output.
10.2.11 Timer Status Register (TSR)
The timer status register (TSR) is an eight-bit read/write register containing flags that indicate
timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or
input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit
in the timer interrupt enable register (TIER), an interrupt request is sent to the CPU. TSR is
initialized to H'F8 or H'78 by a reset and in standby mode. Each ITU channel has one TSR.
Table 10.9 Timer Status Register (TSR)
Channel
0
1
2
3
4
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
Function
TSR indicates input capture, compare match and
overflow status.
Rev. 7.00 Jan 31, 2006 page 249 of 658
REJ09B0272-0700