SH7032 Datasheet, PDF (251/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Table 10.1 ITU Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4
Counter clocks
Internal: φ, φ/2, φ/4, φ/8
External: Independently selectable from TCLKA, TCLKB, TCLKC, and TCLKD
General registers
(output compare/
input capture dual
registers)
GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4
Buffer registers
No
No
No
BRA3, BRB3 BRA4, BRB4
Input/output pins
TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
TIOCA4,
TIOCB4
Output pins
No
No
No
No
TOCXA4,
TOCXB4
Counter clear func- GRA0/GRB0 GRA1/GRB1 GRA2/GRB2 GRA3/GRB3 GRA4/GRB4
tion (compare match
or input capture)
Compare 0
Yes
Yes
Yes
Yes
Yes
match
output
1
Yes
Yes
Yes
Yes
Yes
Toggle Yes
Yes
No
Yes
Yes
output
Input capture
Yes
Yes
Yes
Yes
Yes
function
Synchronization Yes
Yes
Yes
Yes
Yes
PWM mode
Yes
Yes
Yes
Yes
Yes
Reset-synchronized No
No
No
Yes
Yes
PWM mode
Complementary No
No
No
Yes
Yes
PWM mode
Phase counting
No
No
Yes
No
No
mode
Buffer operation No
No
No
Yes
Yes
DMAC activation
GRA0 com- GRA1 com- GRA2 com- GRA3 com- No
pare match or pare match or pare match or pare match or
input capture input capture input capture input capture
Interrupt sources
(three)
• Compare • Compare • Compare • Compare • Compare
match/input match/input match/input match/input match/input
capture A0 capture A1 capture A2 capture A3 capture A4
• Compare • Compare • Compare • Compare • Compare
match/input match/input match/input match/input match/input
capture B0 capture B1 capture B2 capture B3 capture B4
• Overflow • Overflow • Overflow • Overflow • Overflow
Rev. 7.00 Jan 31, 2006 page 225 of 658
REJ09B0272-0700