SH7032 Datasheet, PDF (194/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
For details on bus cycles when external spaces are accessed, see section 8.4, Accessing External
Memory Space, section 8.5, DRAM Interface Operation, and section 8.6, Address/Data
Multiplexed I/O Space Access.
Accesses to on-chip spaces are as follows: On-chip supporting module spaces (area 5 when
address bit A27 is 1) are always 3-state access spaces, regardless of WCR, with no WAIT signal
sampling. Accesses to on-chip ROM (area 0 when MD2–MD0 are 010) and on-chip RAM (area 7
when address bit A27 is 0) are always performed in 1 state, regardless of WCR, with no WAIT
signal sampling.
If the bus timing specifications (t_WTS and t_WTH) are not observed when the WAIT signal is input
in external space access, this will simply mean that WAIT signal assertion and negation will not
be detected, but will not result in misoperation. Note, however, that the inability to detect WAIT
signal assertion may result in a problem with memory access due to insertion of an insufficient
number of waits.
Rev. 7.00 Jan 31, 2006 page 168 of 658
REJ09B0272-0700