SH7032 Datasheet, PDF (74/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
2.5.2 Power-Down State
In addition to the ordinary program execution states, the CPU also has a power-down state in
which CPU operation halts and power consumption is reduced There are two power-down state
modes: sleep mode and standby mode.
Sleep Mode: When the standby bit SBY (in the standby control register, SBYCR) is cleared to 0
and a SLEEP instruction is executed, the CPU switches from program execution state to sleep
mode. In sleep mode, the CPU halts and the contents of its internal registers and the data in on-
chip RAM are stored. The on-chip supporting modules other than the CPU do not halt in sleep
mode.
Sleep mode is cleared by a reset, any interrupt, or a DMA address error; the CPU returns to
ordinary program execution state through the exception handling state.
Software Standby Mode: To enter standby mode, set standby bit SBY (in the standby control
register, SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip
supporting module and oscillator functions are halted. CPU internal register contents and on-chip
RAM data are held.
Standby mode is cleared by a reset or an external NMI interrupt. For resets, the CPU returns to the
ordinary program execution state through the exception handling state when placed in a reset state
during the oscillator settling time. For NMI interrupts, the CPU returns to the ordinary program
execution state through the exception handling state after the oscillator settling time has elapsed.
In this mode, power consumption drops markedly, since the oscillator stops.
Table 2.19 Power-Down State
Mode
Sleep
mode
Conditions
Clock
Execute SLEEP Run
instruction with
SBY bit cleared
to 0 in SBYCR
State
On-Chip CPU
Supporting Regi-
CPU Modules sters
Halted Run
Held
RAM
Held
Standby Execute SLEEP Halted Halted Halted and Held
mode instruction with
initialized*
SBY bit set to 1
in SBYCR
Note: * Differs depending on the supporting module and pin.
Held
I/O
Ports Canceling
Held 1. Interrupt
2. DMA address
error
3. Power-on
reset
4. Manual reset
Held or 1. NMI
high-Z* _{2. Power-on}
(select- _reset
able) _{3. Manual reset}
Rev. 7.00 Jan 31, 2006 page 48 of 658
REJ09B0272-0700