SH7032 Datasheet, PDF (624/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.28 DMA Operation Registers (DMAOR)
DMAC
Start Address: H'5FFFF48
Bus Width: 8/16/32
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
—
—
—
—
—
—
PR1 PR0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
R/W
R/W
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
AE
NMIF DME
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
— R/(W)* R/(W)* R/W
Note: * Only 0 can be written, to clear the flag.
Table A.29 DMAOR Bit Functions
Bit Bit name
Value Description
9,8 Priority mode bits 1, 0 0 0 Priority order is fixed
(Initial value)
(PR1,PR0)
(Channel 0 > channel 3 > channel 2 > channel 1)
0 1 Priority order is fixed (Channel 1 > channel 3 > channel 2 >
channel 0)
1 0 Round-robin priority order (Immediately after reset:
Channel 0 > channel 3 > channel 2 > channel 1)
1 1 External-pin-alternating mode priority order (Immediately
after reset: Channel 3 > channel 2 > channel 1 > channel
0)
2
Address error flag bit 0
(AE)
No errors caused by DMAC
(Initial value)
Clear Condition: Write 0 in AE after reading AE
1
Address error caused by DMAC
1
NMI flag bit (NMIF) 0
No NMI interrupt
(Initial value)
Clear Condition: Write 0 in NMIF after reading NMIF
1
NMI interrupt generated
0
DMA master enable 0
bit (DME)
1
DMA transfer disabled for all channels
DMA transfer enabled for all channels
(Initial value)
Rev. 7.00 Jan 31, 2006 page 598 of 658
REJ09B0272-0700