SH7032 Datasheet, PDF (321/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6.2 Contention between TCNT Word Write and Increment
If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and
TCNT is not incremented. The timing is shown in figure 10.59.
TCNT word write cycle by CPU
T1
T2
T3
CK
Address
Internal write signal
TCNT address
TCNT input clock
TCNT
N
M
TCNT write data
Figure 10.59 Contention between TCNT Word Write and Increment
Rev. 7.00 Jan 31, 2006 page 295 of 658
REJ09B0272-0700