SH7032 Datasheet, PDF (47/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
2.2.3 Immediate Data Format
Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the
MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword
data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
is handled as longword data. Consequently, AND instructions with immediate data always clear
the upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code but rather is stored in a
memory table. The memory table is accessed by an immediate data transfer instruction (MOV)
using the PC relative addressing mode with displacement.
2.3 Instruction Features
2.3.1 RISC-Type Instruction Set
All instructions are RISC type. Their features are as follows:
16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more
efficient.
One Instruction/Cycle: Basic instructions can be executed in one cycle using a pipeline system.
One-cycle instructions are executed in 50 ns at 20 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations (handled as longword data).
Table 2.2 Sign Extension of Word Data
SH7000 Series CPU
Description
Conventional CPUs
MOV.W
@(disp,PC),R1
ADD R1,R0
...........
.DATA.W H'1234
Data is sign-extended to 32 bits, and
R1 becomes H'00001234. It is next
operated upon by an ADD
instruction.
ADD.W
#H'1234,R0
Note: The address of the immediate data is accessed by @(disp, PC).
Rev. 7.00 Jan 31, 2006 page 21 of 658
REJ09B0272-0700