SH7032 Datasheet, PDF (368/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 12 Watchdog Timer (WDT)
12.2.2 Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an eight-bit read/write register. TCSR differs from
other registers in being more difficult to write. See section 12.2.4, Register Access, for details. Its
functions include selecting the timer mode and clock source. Bits 7–5 are initialized to 000 by a
reset and in standby mode. Bits 2–0 are initialized to 000 by a reset, but retain their values in
standby mode.
Bit
7
6
5
4
OVF WT/IT TME
—
Initial value
0
0
0
1
Read/Write
R/(W)* R/W R/W
—
Note: * Only 0 can be written, to clear the flag.
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W R/W R/W
Bit 7—Overflow Flag (OVF): OVF indicates that TCNT has overflowed from H'FF to H'00 in
interval timer mode. It is not set in watchdog timer mode.
Bit 7: OVF
0
1
Description
No overflow of TCNT in interval timer mode
Cleared by reading OVF, then writing 0 in OVF
TCNT overflow in interval timer mode
(Initial value)
Bit 6—Timer Mode Select (WT/IT): WT/IT selects whether to use the WDT as a watchdog timer
or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on the mode selected.
Bit 6: WT/IT
0
1
Description
Interval timer mode: interval timer interrupt to the CPU when TCNT overflows
(Initial value)
Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR), describes
in detail what happens when TCNT overflows in watchdog timer mode.
Rev. 7.00 Jan 31, 2006 page 342 of 658
REJ09B0272-0700