SH7032 Datasheet, PDF (202/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
The maximum number of states from BREQ input to bus release are used when B is a cycle
comprising the maximum number of states for which the bus is not released; the number of states
is the maximum number of states for which bus is not released + approx. 4.5 states.
The maximum number of states for which the bus is not released requires careful investigation.
CK
Bus cycle
A
BREQ
BACK
t_BRQS
B
t_{BACD1 Bus release}
Figure 8.43 When BREQ is Input without Satisfying t_BRQS
1. Cycles in which bus is not released
a. One bus cycle
The bus is never released during one bus cycle. For example, in the case of a longword
read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit
ordinary space, as shown in figure 8.44. The bus is not released between these accesses.
Assuming one memory access to require 2 states, the bus is not released for a period of 8
states.
8 bits 8 bits 8 bits 8 bits
Cycle during which
bus is not released
Figure 8.44 One Bus Cycle
b. TAS instruction read cycle and write cycle
The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45).
The TAS instruction read cycle and write cycle should be regarded as one bus cycle during
which the bus is not released.
Read cycle Write cycle
Cycle during which bus is
not released (1 bus cycle)
Figure 8.45 TAS Instruction Read Cycle and Write Cycle
Rev. 7.00 Jan 31, 2006 page 176 of 658
REJ09B0272-0700