SH7032 Datasheet, PDF (277/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bit 0—Input Capture/Compare Match A (IMFA): IMFA indicates a GRA compare match or
input capture.
Bit 0: IMFA
0
1
Description
Clearing condition:
Read IMFA when IMFA = 1, then write 0 in IMFA
(Initial value)
DMAC is activated by an IMIA interrupt (only channels 0–3)
Setting conditions:
• GRA is functioning as an output compare register and TCNT = GRA
• GRA is functioning as an input capture register and the value of TCNT is
transferred to GRA by an input capture signal
10.2.12 Timer Interrupt Enable Register (TIER)
The timer status interrupt enable register (TIER) is an eight-bit read/write register that controls
enabling/disabling of overflow interrupt requests and general register compare match/input capture
interrupt requests. TIER is initialized to H'F8 or H'78 by a reset and in standby mode. Each ITU
channel has one TIER.
Table 10.10 Timer Interrupt Enable Register (TIER)
Channel
0
1
2
3
4
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
Function
TIER controls interrupt enabling/disabling
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE IMIEB IMIEA
Initial value
*
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: * Undefined
Bits 7–3—Reserved: Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value to
bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
Rev. 7.00 Jan 31, 2006 page 251 of 658
REJ09B0272-0700