SH7032 Datasheet, PDF (79/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Exception Handling
4.1.2 Exception Handling Operation
Exception sources are detected at the times indicated in table 4.1, whereupon handling starts.
Table 4.1 Exception Source Detection and Start of Handling
Exception Type
Source Detection and Start of Handling
Reset
Power-on
Low-to-high transition at RES pin when NMI is high
Manual
Low-to-high transition at RES pin when NMI is low
Address error
Detected when instruction is decoded and starts after the
instruction that was executing prior to this point is completed.
Interrupt
Detected when instruction is decoded and starts after the
instruction that was executing prior to this point is completed.
Instruction Trap instruction Starts when a trap instruction (TRAPA) is executed.
General illegal Starts when undefined code is decoded at a position other than
instruction
directly after a delayed branch instruction (a delay slot).
Illegal slot
instruction
Starts when undefined code or an instruction that rewrites the PC
is decoded directly after a delayed branch instruction (in a delay
slot).
When exception handling begins, the CPU operates as follows:
Resets: The initial values of the program counter (PC) and stack pointer (SP) are read from the
exception vector table (the respective PC and SP values are H'00000000 and H'00000004 for a
power-on reset and H'00000008 and H'0000000C for a manual reset). For more information on the
exception vector table, see section 4.1.3, Exception Vector Table. Next, the vector base register
(VBR) is cleared to zero and interrupt mask bits (I3–I0) in the status register (SR) are set to 1111.
Program execution starts from the PC address read from the exception vector table.
Address Errors, Interrupts and Instructions: SR and PC are pushed onto the stack indicated in
R15. For interrupts, the interrupt priority level is written in the interrupt mask bits (I3–I0). For
address errors and instructions, bits I3–I0 are not affected. Next, the start address is fetched from
the exception vector table, and program execution starts from this address.
Rev. 7.00 Jan 31, 2006 page 53 of 658
REJ09B0272-0700