SH7032 Datasheet, PDF (301/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.4.6 Complementary PWM Mode
In complementary PWM mode, three pairs of complementary, non-overlapping, positive and
negative PWM waveforms can be obtained using channels 3 and 4. In complementary PWM
mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins become PWM
output pins and TCNT3 and TCNT4 become up-counters. Table 10.14 shows the PWM output
pins used and table 10.15 shows the settings of the registers used.
Table 10.14 Output Pins for Complementary PWM Mode
Channel
3
4
Output Pin
TIOCA3
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TOCXB4
Description
PWM output 1
PWM output 1' (non-overlapping negative-phase waveform
of PWM output 1)
PWM output 2
PWM output 2' (non-overlapping negative-phase waveform
of PWM output 2)
PWM output 3
PWM output 3' (non-overlapping negative-phase waveform
of PWM output 3)
Table 10.15 Register Settings for Complementary PWM Mode
Register Setting
TCNT3 Initial setting of non-overlap cycle (difference with TCNT4)
TCNT4 Initial setting of H'0000
GRA3 Sets upper limit of TCNT3–1
GRB3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins
GRA4 Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins
GRB4 Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins
Procedure for Selecting Complementary PWM Mode (Figure 10.33):
1. Clear the STR3 and STR4 bits in TSTR to halt the timer counters. Complementary PWM
mode must be set while TCNT3 and TCNT4 are halted.
2. Set bits TPSC2–TPSC0 in TCR to select the same counter clock source for channels 3 and 4. If
an external clock source is selected, select the external clock edge with bits CKEG1 and
CKEG0 in TCR. Do not select any counter clear source with bits CCLR1 and CCLR0 in TCR.
Rev. 7.00 Jan 31, 2006 page 275 of 658
REJ09B0272-0700