SH7032 Datasheet, PDF (24/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

A.2.10 Timer Start Register (TSTR) ITU........................................................................ 577
A.2.11 Timer Synchronization Register (TSNC) ITU..................................................... 578
A.2.12 Timer Mode Register (TMDR) ITU .................................................................... 580
A.2.13 Timer Function Control Register (TFCR) ITU.................................................... 581
A.2.14 Timer Control Registers 0–4 (TCR0–TCR4) ITU ............................................... 582
A.2.15 Timer I/O Control Registers 0–4 (TIOR0–TIOR4) ITU...................................... 583
A.2.16 Timer Interrupt Enable Registers 0–4 (TIER0–TIER4) ITU ............................... 584
A.2.17 Timer Status Registers 0–4 (TSR0–TSR4) ITU .................................................. 585
A.2.18 Timer Counter 0–4 (TCNT0–TCNT4) ITU......................................................... 586
A.2.19 General Registers A0–4 (GRA0–GRA4) ITU ..................................................... 587
A.2.20 General Registers B0–4 (GRB0–GRB4) ITU...................................................... 588
A.2.21 Buffer Registers A3, 4 (BRA3, BRA4) ITU........................................................ 589
A.2.22 Buffer Registers B3, 4 (BRB3, BRB4) ITU ........................................................ 590
A.2.23 Timer Output Control Register (TOCR) ITU ...................................................... 591
A.2.24 DMA Source Address Registers 0–3 (SAR0–SAR3) DMAC ............................. 592
A.2.25 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMAC..................... 593
A.2.26 DMA Transfer Count Registers 0–3 (TCR0–TCR3) DMAC .............................. 594
A.2.27 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMAC...................... 595
A.2.28 DMA Operation Registers (DMAOR) DMAC .................................................... 598
A.2.29 Interrupt Priority Setting Register A (IPRA) INTC ............................................. 599
A.2.30 Interrupt Priority Setting Register B (IPRB) INTC ............................................. 600
A.2.31 Interrupt Priority Setting Register C (IPRC) INTC ............................................. 601
A.2.32 Interrupt Priority Setting Register D (IPRD) INTC ............................................. 602
A.2.33 Interrupt Priority Setting Register E (IPRE) INTC.............................................. 603
A.2.34 Interrupt Control Register (ICR) INTC................................................................ 604
A.2.35 Break Address Register H (BARH) UBC............................................................ 605
A.2.36 Break Address Register L (BARL) UBC............................................................. 606
A.2.37 Break Address Mask Register H (BAMRH) UBC............................................... 607
A.2.38 Break Address Mask Register L (BAMRL) UBC ............................................... 608
A.2.39 Break Bus Cycle Register (BBR) UBC ............................................................... 609
A.2.40 Bus Control Register (BCR) BSC........................................................................ 610
A.2.41 Wait State Control Register 1 (WCR1) BSC ....................................................... 611
A.2.42 Wait State Control Register 2 (WCR2) BSC ....................................................... 612
A.2.43 Wait State Control Register 3 (WCR3) BSC ....................................................... 614
A.2.44 DRAM Area Control Register (DCR) BSC ......................................................... 615
A.2.45 Parity Control Register (PCR) BSC..................................................................... 617
A.2.46 Refresh Control Register (RCR) BSC.................................................................. 618
A.2.47 Refresh Timer Control/Status Register (RTCSR) BSC ....................................... 619
A.2.48 Refresh Timer Counter (RTCNT) BSC ............................................................... 620
A.2.49 Refresh Timer Constant Register (RTCOR) BSC................................................ 621
Rev. 7.00 Jan 31, 2006 page xxiv of xxvi