SH7032 Datasheet, PDF (93/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Interrupt Controller (INTC)
Section 5 Interrupt Controller (INTC)
5.1 Overview
The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt
requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These
registers handle interrupt requests according to user-specified priorities.
5.1.1 Features
The interrupt controller has the following features:
• 16 settable priority levels: Five interrupt priority registers can set 16 levels of interrupt
priorities for IRQ and on-chip supporting module interrupt sources.
• NMI noise canceller function: INTC has an NMI input level bit that indicates the NMI pin
status. By reading this bit in the interrupt exception handling routine, the pin status can be
checked for use in a noise canceller function.
• The interrupt controller can notify external devices (via the IRQOUT pin) that an on-chip
interrupt has occurred. In this way an external device can, for example, be informed if an on-
chip interrupt occurs while the chip is operating in bus-released mode and the bus has been
requested.
5.1.2 Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
Rev. 7.00 Jan 31, 2006 page 67 of 658
REJ09B0272-0700