SH7032 Datasheet, PDF (105/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Interrupt Controller (INTC)
5.4.2 Stack after Interrupt Exception Handling
Figure 5.3 shows the stack after interrupt exception handling.
Address
4n–8
4n–6
4n–4
4n–2
4n
PC^*1
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SP^*2
Notes: Bus width is 16 bits.
1. PC stores the start address of the next instruction (return instruction) after the
executed instruction.
2. The value of SP must always be a multiple of four.
Figure 5.3 Stack after Interrupt Exception Handling
Rev. 7.00 Jan 31, 2006 page 79 of 658
REJ09B0272-0700