SH7032 Datasheet, PDF (66/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Table 2.17 System Control Instructions
Instruction
Instruction Code
Operation
CLRT
CLRMAC
LDC Rm,SR
LDC Rm,GBR
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0→T
0 → MACH, MACL
Rm → SR
Rm → GBR
LDC Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 →
Rm
LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 →
Rm
LDS.L @Rm+,PR
NOP
0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm
0000000000001001 No operation
RTE
0000000000101011 Delayed branch, stack area →
PC/SR
SETT
SLEEP
0000000000011000 1 → T
0000000000011011 Sleep
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC.L SR,@–Rn
STC.L GBR,@–Rn
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
SR → Rn
GBR → Rn
VBR → Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
STC.L VBR,@–Rn 0100nnnn00100011 Rn–4 → Rn, VBR → (Rn)
STS MACH,Rn 0000nnnn00001010 MACH → Rn
Note: * The number of execution states before the chip enters the sleep state.
Execution
Cycles
1
1
1
1
1
3
3
3
1
1
1
1
1
1
1
4
1
3*
1
1
1
2
2
2
1
T Bit
0
—
LSB
—
—
LSB
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
Rev. 7.00 Jan 31, 2006 page 40 of 658
REJ09B0272-0700