SH7032 Datasheet, PDF (665/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.64 TPC Output Mode Register (TPMR)
Start Address: H'5FFFFF0
Bus Width: 8/16
Bit
Initial value
Read/Write
7
6
5
4
—
—
—
—
1
1
1
1
—
—
—
—
TPC
3
2
1
0
G3NOV G2NOV G1NOV G0NOV
0
0
0
0
R/W R/W R/W R/W
Table A.65 TPMR Bit Functions
Bit Bit Name
3 Group 3 non-
overlap
(G3NOV)
2 Group 2 non-
overlap
(G2NOV)
1 Group 1 non-
overlap
(G1NOV)
0 Group 0 non-
overlap
(G0NOV)
Value Description
0
TPC output group 3 operates normally (the output value is
updated at every compare match A of the selected ITU)
(Initial value)
1
TPC output group 3 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
0
TPC output group 2 operates normally (the output value is
updated at every compare match A of the selected ITU)
(Initial value)
1
TPC output group 2 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
0
TPC output group 1 operates normally (the output value is
updated at every compare match A of the selected ITU)
(Initial value)
1
TPC output group 1 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
0
TPC output group 0 operates normally (the output value is
updated at every compare match A of the selected ITU)
(Initial value)
1
TPC output group 0 operates in non-overlap mode (1 output and
0 output can be performed independently upon compare
matches A and B of the selected ITU)
Rev. 7.00 Jan 31, 2006 page 639 of 658
REJ09B0272-0700