SH7032 Datasheet, PDF (369/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 12 Watchdog Timer (WDT)
Bit 5—Timer Enable (TME): TME enables or disables the timer.
Bit 5: TME
0
1
Description
Timer disabled: TCNT is initialized to H'00 and count-up stops
(Initial value)
Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is
generated when TCNT overflows.
Bits 4 and 3—Reserved): These bits are always read as 1. The write value should always be 1.
Bits 2–0—Clock Select 2–0 (CKS2–CKS0): CKS2–CKS0 select one of eight internal clock
sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system
clock (φ).
Description
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source
Overflow Interval* (φ = 20 MHz)
0
0
0
φ/2 (Initial value) 25.6 µs
0
0
1
φ/64
819.2 µs
0
1
0
φ/128
1.6 ms
0
1
1
φ/256
3.3 ms
1
0
0
φ/512
6.6 ms
1
0
1
φ/1024
13.1 ms
1
1
0
φ/4096
52.4 ms
1
1
1
φ/8192
104.9 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an
overflow occurs.
12.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an eight-bit read/write register that controls output of the reset signal generated by
timer counter (TCNT) overflow and selects the internal reset signal type. RSTCSR differs from
other registers in that it is more difficult to write. See section 12.2.4, Notes on Register Access, for
details. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not
initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F
in standby mode.
Rev. 7.00 Jan 31, 2006 page 343 of 658
REJ09B0272-0700