SH7032 Datasheet, PDF (45/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
2.1.3 System Registers
System registers consist of four 32-bit registers: multiply and accumulate registers high and low
(MACH and MACL), procedure register (PR), and program counter (PC). The multiply and
accumulate registers store the results of multiply and accumulate operations. The procedure
register stores the return address for a subroutine procedure. The program counter stores program
addresses to control the flow of the processing.
31
9
0 ^{Multiply and accumulate (MAC) registers}
(Sign extended)
MACL
MACH
high and low (MACH, MACL): Store the
results of multiply and accumulate opera-
tions. MACH is sign-extended when read
because only the lowest 10 bits are valid.
31
PR
0
Procedure register (PR): Stores the return
address for a subroutine procedure.
31
PC
0 _{Program counter (PC): Indicates the}
fourth byte (second instruction) after
the current instruction.
Figure 2.3 System Registers
2.1.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset.
Table 2.1 Initial Values of Registers
Classification Register
General registers R0–R14
R15 (SP)
Control registers SR
System registers
GBR
VBR
MACH, MACL, PR
PC
Initial Value
Undefined
Value of the stack pointer in the vector address table
Bits I3–I0 are 1111(H'F), reserved bits are 0, and other
bits are undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector address table
Rev. 7.00 Jan 31, 2006 page 19 of 658
REJ09B0272-0700