SH7032 Datasheet, PDF (63/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Instruction
Instruction Code
Operation
Execution
Cycles
T Bit
EXTS.W Rm,Rn
0110nnnnmmmm1111 A word in Rm is sign- 1
—
extended → Rn
EXTU.B Rm,Rn
0110nnnnmmmm1100 A byte in Rm is zero- 1
—
extended → Rn
EXTU.W Rm,Rn
0110nnnnmmmm1101 A word in Rm is zero- 1
—
extended → Rn
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of 3/(2)*
—
(Rn) × (Rm) + MAC →
MAC
16 × 16 + 42 → 42-bit
MULS Rm,Rn
0010nnnnmmmm1111 Signed operation of 1–3*
—
Rn × Rm → MAC
16 × 16 → 32-bit
MULU Rm,Rn
0010nnnnmmmm1110 Unsigned operation of 1–3*
—
Rn × Rm → MAC
16 × 16 → 32-bit
NEG Rm,Rn
0110nnnnmmmm1011 0–Rm → Rn
1
—
NEGC Rm,Rn
0110nnnnmmmm1010 0–Rm–T → Rn,
1
Borrow → T
Borrow
SUB Rm,Rn
0011nnnnmmmm1000 Rn–Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn–Rm–T → Rn,
1
Borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn–Rm → Rn,
1
Underflow → T
Underflow
Note: * The normal minimum number of cycles (numbers in parenthesis represent the number of
cycles when there is contention with preceding or following instructions).
Rev. 7.00 Jan 31, 2006 page 37 of 658
REJ09B0272-0700