SH7032 Datasheet, PDF (317/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Timing of Setting IMFA, IMFB for Input Capture: IMFA and IMFB are set to 1 by an input
capture signal. At this time, the TCNT contents are transferred to GR. Figure 10.55 shows the
timing.
CK
Input
capture
signal
IMF
TCNT
GR
N
N
IMI
Figure 10.55 Timing of Setting IMFA and IMFB for Input Capture
Timing of Setting Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from H'FFFF
to H'0000 or underflows from H'0000 to H'FFFF. Figure 10.56 shows the timing.
CK
TCNT
Overflow
signal
OVF
H' FFFF
H' 0000
OVI
Figure 10.56 Timing of Setting OVF
Rev. 7.00 Jan 31, 2006 page 291 of 658
REJ09B0272-0700