SH7032 Datasheet, PDF (600/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Bit Bit name
Value Description
2 Transmit end 0
(TEND)
Indicates that transmission is in progress
Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1;
(2) Data written to TDR by DMAC
1
Indicates that transmission has ended
(Initial value)
Set Conditions: (1) Reset or standby mode; (2) TE bit in SCR is 0;
(3) TDRE = 1 when the final bit of a 1-byte serial transmit character
is transmitted
1 Multiprocessor 0
bit (MPB)
Indicates that data with multiprocessor bit = 0 has been received
(Initial value)
1
Indicates that data with multiprocessor bit = 1 has been received
0 Multiprocessor 0
bit transfer
1
(MPBT)
0 transmitted as the multiprocessor bit
1 transmitted as the multiprocessor bit
(Initial value)
A.2.6 Receive Data Register (RDR)
SCI
Start Address: H'5FFFEC5 (channel 0), H'5FFFECD (channel 1)
Bus Width: 8/16
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit Bit name
7–0 (Receive serial data storage)
Description
Store the serial data received
Rev. 7.00 Jan 31, 2006 page 574 of 658
REJ09B0272-0700