SH7032 Datasheet, PDF (606/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.12 Timer Mode Register (TMDR)
ITU
Start Address: H'5FFFF02
Bus Width: 8
Bit
7
—
Initial value
*
Read/Write
—
Note: * Undetermined
6
MDF
0
R/W
5
FDIR
0
R/W
4
PWM4
0
R/W
3
PWM3
0
R/W
2
PWM2
0
R/W
1
PWM1
0
R/W
0
PWM0
0
R/W
Table A.13 TMDR Bit Functions
Bit Bit name
6 Phase counting mode (MDF)
5 Flag direction (FDIR)
4 PWM mode 4 (PWM4)
3 PWM mode 3 (PWM3)
2 PWM mode 2 (PWM2)
1 PWM mode 1 (PWM1)
0 PWM mode 0 (PWM0)
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Channel 2 operates normally
(Initial value)
Channel 2 in phase count mode
OVF of TSR2 set to 1 when TCNT2 overflows or
underflows
(Initial value)
OVF in TSR2 set to 1 when TCNT2 overflows
Channel 4 operates normally
(Initial value)
Channel 4 in PWM mode
Channel 3 operates normally
(Initial value)
Channel 3 in PWM mode
Channel 2 operates normally
(Initial value)
Channel 2 in PWM mode
Channel 1 operates normally
(Initial value)
Channel 1 in PWM mode
Channel 0 operates normally
(Initial value)
Channel 0 in PWM mode
Rev. 7.00 Jan 31, 2006 page 580 of 658
REJ09B0272-0700