SH7032 Datasheet, PDF (320/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6 Notes and Precautions
This section describes contention and other matters requiring special attention during ITU
operation.
10.6.1 Contention between TCNT Write and Clear
If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes
priority and the write is not performed. The timing is shown in figure 10.58.
TCNT write cycle by CPU
T1
T2
T3
CK
Address
Internal write signal
TCNT address
Counter clear signal
TCNT
N
H' 0000
Figure 10.58 Contention between TCNT Write and Clear
Rev. 7.00 Jan 31, 2006 page 294 of 658
REJ09B0272-0700