SH7032 Datasheet, PDF (609/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.15 Timer I/O Control Registers 0–4 (TIOR0–TIOR4)
ITU
Start Address: H'5FFFF05 (channel 0), H'5FFFF0F (channel 1), H'5FFFF19 (channel 2),
H'5FFFF23 (channel 3), H'5FFFF33 (channel 4)
Bus Width: 8
Bit
7
6
5
4
3
2
1
0
—
IOB2 IOB1 IOB0
—
IOA2 IOA1 IOA0
Initial value
*
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: * Undetermined
Table A.16 TIO0–TIO4 Bit Functions
Bit Bit name
6–4 I/O control B2–0
(IOB2–IOB0)
2–0 I/O control A2–0
(IOA2–IOA0)
Note: * 0 or 1
Value
000
001
010
011
100
101
11*
000
001
010
011
100
101
11*
Description
GRB is output
compare register
GRB is input
capture register
GRA is output
compare register
GRA is input
capture register
Pin output due to compare match
disabled
(Initial value)
0 output on GRB compare match
1 output on GRB compare match
Toggle output on GRB compare match
(1 output on channel 2 only)
Input capture to GRB on rising edge
Input capture to GRB on falling edge
Input capture on both rising and falling
edges
Pin output due to compare match
disabled
(Initial value)
0 output on GRA compare match
1 output on GRA compare match
Toggle output on GRA compare match
(1 output on channel 2 only)
Input capture to GRA on rising edge
Input capture to GRA on falling edge
Input capture on both rising and falling
edges
Rev. 7.00 Jan 31, 2006 page 583 of 658
REJ09B0272-0700