SH7032 Datasheet, PDF (18/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10.1.3 Input/Output Pins ................................................................................................. 231
10.1.4 Register Configuration......................................................................................... 232
10.2 ITU Register Descriptions ................................................................................................ 234
10.2.1 Timer Start Register (TSTR) ............................................................................... 234
10.2.2 Timer Synchro Register (TSNC) ......................................................................... 235
10.2.3 Timer Mode Register (TMDR) ............................................................................ 237
10.2.4 Timer Function Control Register (TFCR)............................................................ 239
10.2.5 Timer Output Control Register (TOCR) .............................................................. 241
10.2.6 Timer Counters (TCNT) ...................................................................................... 242
10.2.7 General Registers A and B (GRA and GRB)....................................................... 243
10.2.8 Buffer Registers A and B (BRA, BRB) ............................................................... 244
10.2.9 Timer Control Register (TCR)............................................................................. 245
10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 247
10.2.11 Timer Status Register (TSR)................................................................................ 249
10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. 251
10.3 CPU Interface.................................................................................................................... 253
10.3.1 16-Bit Accessible Registers ................................................................................. 253
10.3.2 8-Bit Accessible Registers ................................................................................... 255
10.4 Operation .......................................................................................................................... 256
10.4.1 Overview.............................................................................................................. 256
10.4.2 Basic Functions.................................................................................................... 257
10.4.3 Synchronizing Mode............................................................................................ 266
10.4.4 PWM Mode ......................................................................................................... 268
10.4.5 Reset-Synchronized PWM Mode......................................................................... 272
10.4.6 Complementary PWM Mode............................................................................... 275
10.4.7 Phase Counting Mode .......................................................................................... 282
10.4.8 Buffer Mode......................................................................................................... 284
10.4.9 ITU Output Timing .............................................................................................. 289
10.5 Interrupts ........................................................................................................................... 290
10.5.1 Timing of Setting Status Flags............................................................................. 290
10.5.2 Status Flag Clear Timing ..................................................................................... 292
10.5.3 Interrupt Sources and DMAC Activation ............................................................ 293
10.6 Notes and Precautions....................................................................................................... 294
10.6.1 Contention between TCNT Write and Clear........................................................ 294
10.6.2 Contention between TCNT Word Write and Increment ...................................... 295
10.6.3 Contention between TCNT Byte Write and Increment........................................ 296
10.6.4 Contention between GR Write and Compare Match............................................ 297
10.6.5 Contention between TCNT Write and Overflow/Underflow............................... 298
10.6.6 Contention between General Register Read and Input Capture........................... 299
Rev. 7.00 Jan 31, 2006 page xviii of xxvi