SH7032 Datasheet, PDF (132/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
8.1.4 Register Configuration
The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM
interface, and parity check.
Table 8.2 Register Configuration
Name
Abbr.
R/W Initial Value Address*¹ Bus width
Bus control register
BCR
R/W H'0000
H'5FFFFA0 8,16,32
Wait state control register 1 WCR1
R/W H'FFFF
H'5FFFFA2 8,16,32
Wait state control register 2 WCR2
R/W H'FFFF
H'5FFFFA4 8,16,32
Wait state control register 3 WCR3
R/W H'F800
H'5FFFFA6 8,16,32
DRAM area control register DCR
R/W H'0000
H'5FFFFA8 8,16,32
Parity control register
Refresh control register
Refresh timer control/status
register
Refresh timer counter
Refresh time constant
register
PCR
RCR
RTCSR
RTCNT
RTCOR
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'00FF
H'5FFFFAA
H'5FFFFAC
H'5FFFFAE
8,16,32
8,16,32*²
8,16,32*²
H'5FFFFB0
H'5FFFFB2
8,16,32*²
8,16,32*²
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
2. Write only with word transfer instructions. See section 8.2.11, Notes on Register
Access, for details on writing.
Rev. 7.00 Jan 31, 2006 page 106 of 658
REJ09B0272-0700