SH7032 Datasheet, PDF (147/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
8.2.7 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that selects the
clock input to the refresh timer counter (RTCNT) and controls compare match interrupts (CMI). It
is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby
mode.
To prevent RTCSR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'A5 is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
CMF CMIE CKS2 CKS1 CKS0
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
—
—
—
Bits 15–8—Reserved: These bits are always read as 0.
Bit 7—Compare Match Flag (CMF): Indicates whether the values of RTCNT and the refresh
time constant register (RTCOR) match. When 0, the value of RTCNT and RTCOR do not match;
when 1, the value of RTCNT and RTCOR match.
Bit 7: CMF
0
1
Description
RTCNT value does not equal RTCOR value
(Initial value)
To clear CMF, the CPU must read CMF after it has been set to 1, then write a 0
in this bit
RTCNT value is equal to RTCOR value
Rev. 7.00 Jan 31, 2006 page 121 of 658
REJ09B0272-0700