SH7032 Datasheet, PDF (243/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9.4 Examples of Use
Section 9 Direct Memory Access Controller (DMAC)
9.4.1 DMA Transfer between On-Chip RAM and Memory-Mapped External Device
In the following example, data is transferred from on-chip RAM to a memory-mapped external
device with an input capture A/compare match A interrupt (IMIA0) from channel 0 of the 16-bit
integrated timer pulse unit (ITU) as the transfer request signal. The transfer is performed by
DMAC channel 3. Table 9.7 shows the transfer conditions and register values.
Table 9.7 Transfer Conditions and Register Settings for Transfer Between On-Chip RAM
and Memory-Mapped External Device
Transfer Conditions
Transfer source: on-chip RAM
Transfer destination: memory-mapped external device
Number of transfers: 8
Transfer destination address: fixed
Transfer source address: incremented
Transfer request source (transfer request signal): ITU channel
0 (IMIA0)
Bus mode: cycle-steal
Transfer unit: byte
DEI interrupt request generated at end of transfer (channel 3
enabled for transfer)
Channel priority order: fixed (0 > 3 > 2 > 1) (all channels
enabled for transfer)
Register
SAR3
DAR3
TCR3
CHCR3
Setting
H'FFFFE00
Destination address
H'0008
H'1805
DMAOR H'0001
Rev. 7.00 Jan 31, 2006 page 217 of 658
REJ09B0272-0700