SH7032 Datasheet, PDF (345/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
Bits 3–0—Next Data 3–0 (NDR3–NDR0): NDR3–NDR0 store the next output data for TPC
output group 0.
Bit
Initial value
Read/Write
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
Address H'5FFFFF7
Bits 7–0—Reserved: These bits are always read as 1. The write value should always be 1.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
Different Triggers for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered
by different compare matches, the address of the upper 4 bits of NDRA (group 1) is H'5FFFFF5
and the address of the lower 4 bits of NDRA (group 0) is H'5FFFFF7. Bits 3–0 of address
H'5FFFFF5 and bits 7–4 of address H'5FFFFF7 are reserved bits. The write value should always
be 1. These bits are always read as 1.
Address H'5FFFFF5
Bits 7–4—Next Data 7–4 (NDR7–NDR4): NDR7–NDR4 store the next output data for TPC
output group 1.
Bits 3–0—Reserved: These bits are always read as 1. The write value should always be 1.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
NDR7 NDR6 NDR5 NDR4
—
—
—
—
0
0
0
0
1
1
1
1
R/W
R/W
R/W
R/W
—
—
—
—
Address H'5FFFFF7
Bits 7–4—Reserved: These bits are always read as 1. The write value should always be 1.
Rev. 7.00 Jan 31, 2006 page 319 of 658
REJ09B0272-0700