SH7032 Datasheet, PDF (27/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 1 Overview
Section 1 Overview
1.1 SuperH Microcomputer Features
SuperH microcomputers (SH7000 series) comprise a new generation of reduced instruction set
computers (RISC) in which a Renesas-original CPU and the peripheral functions required for
system configuration are integrated onto a single chip.
The CPU has a RISC-type instruction set. Most instructions can be executed in one system clock
cycle, which strikingly improves instruction execution speed. In addition, the CPU has a 32-bit
internal architecture for enhanced data-processing ability. As a result, the CPU enables high-
performance systems to be constructed with advanced functionality at low cost, even in
applications such as realtime control that require very high speeds, an impossibility with
conventional microcomputers.
SH microcomputers include peripheral functions such as large-capacity ROM, RAM, a direct
memory access controller (DMAC), timers, a serial communication interface (SCI), an A/D
converter, an interrupt controller (INTC), and I/O ports. External memory access support functions
enable direct connection to SRAM and DRAM. These features can drastically reduce system cost.
For on-chip ROM, masked ROM or electrically programmable ROM (PROM) can be selected.
The PROM version can be programmed by users with a general-purpose PROM programmer.
Table 1.1 lists the features of the SH microcomputers (SH7032 and SH7034).
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REJ09B0272-0700