SH7032 Datasheet, PDF (67/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Instruction
Instruction Code
Operation
Execution
Cycles
T Bit
STS MACL,Rn 0000nnnn00011010 MACL → Rn
1
—
STS PR,Rn
0000nnnn00101010 PR → Rn
1
—
STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn) 1
—
STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn) 1
—
STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn)
1
—
TRAPA #imm
11000011iiiiiiii PC/SR → stack area,
8
—
(imm × 4 + VRR) → PC
Notes: The execution cycles shown in the table are minimums.
The actual number of cycles may be increased:
1. When contention occurs between instruction fetches and data access
2. When the destination register of the load instruction (memory → register) and the
register used by the next instruction are the same.
Rev. 7.00 Jan 31, 2006 page 41 of 658
REJ09B0272-0700