SH7032 Datasheet, PDF (434/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Serial Communication Interface (SCI)
Simultaneous Multiple Receive Errors: Table 13.13 indicates the state of the SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR
contents cannot be transferred to RDR, so receive data is lost.
Table 13.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags
Receive Error Status
RDRF ORER FER
PER
Overrun error
1
1
0
0
Framing error
0
0
1
0
Parity error
0
0
0
1
Overrun error + framing error
1
1
1
0
Overrun error + parity error
1
1
0
1
Framing error + parity error
0
0
1
1
Overrun error + framing error + parity 1
error
1
1
1
O: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
Receive Data
Transfer
RSR → RDR
X
O
O
X
X
O
X
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI
receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Sending a Break Signal: When TE is cleared to 0 the TxD pin becomes an I/O port, the level and
direction (input or output) of which are determined by the data register (DR) of the I/O port and
the control register (CR) of the PFC. This feature can be used to send a break signal. The DR
value substitutes for the mark state until the PFC setting is performed. The DR bits should
therefore be set as an output port that outputs 1 beforehand. To send a break signal during serial
transmission, clear the DR bit to 0, and select output port as the TxD pin function by the PFC.
When TE is cleared to 0, the transmitter is initialized, regardless of its current state.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set
to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE
to 0 does not clear the receive error flags.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous
mode, the SCI operates on a base clock of 16 times the bit rate frequency. In receiving, the SCI
Rev. 7.00 Jan 31, 2006 page 408 of 658
REJ09B0272-0700