SH7032 Datasheet, PDF (330/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6.13 Clearing Complementary PWM Mode
Figure 10.69 shows the procedure for clearing complementary PWM mode. First, reset
combination mode bits CMD1 and CMD0 in the timer function control register (TFCR) from 10 to
either 00 or 01. The mode will switch from complementary PWM mode to normal operating
mode. Next, wait for at least 1 cycle of the counter input clock being used for channels 3 and 4 and
then clear counter start bits STR3 and STR4 in the timer start register (TSTR). The channel 3 and
4 counters, TCNT3 and TCNT4, will stop counting. Clearing complementary PWM mode by any
other procedure may result in changes other than those set for the output waveform when
complementary PWM mode is set again.
Complementary PWM mode
Clear complementary
PWM mode
1. Clear the CMD1 bit in TFCR to 0 to set
channels 3 and 4 for normal operation
Halt count
Normal operation
2. Wait at least 1 clock cycle after setting
channels 3 and 4 for normal operation and
then clear the STR3 and STR4 bits in TSTR
to 0 to halt the TCNT3 and TCNT4 counters
Figure 10.69 Clearing Complementary PWM Mode
10.6.14 Note on Counter Clearing by Input Capture
If TCNT is cleared (to H'0000) by input capture when its value is H'FFFF, overflow will not
occur.
Rev. 7.00 Jan 31, 2006 page 304 of 658
REJ09B0272-0700