SH7032 Datasheet, PDF (260/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Channel Name
Abbrevi-
ation
R/W
Initial
Value
Access
Address*¹ Size
4
General register B4
GRB4 R/W H'FF
H'5FFFF3A 8, 16, 32
H'5FFFF3B 8, 16, 32
Buffer register A4
BRA4 R/W H'FF
H'5FFFF3C 8, 16, 32
H'5FFFF3D 8, 16, 32
Buffer register B4
BRB4 R/W H'FF
H'5FFFF3E 8, 16, 32
H'5FFFF3F 8, 16, 32
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
2. Only 0 can be written to clear flags.
10.2 ITU Register Descriptions
10.2.1 Timer Start Register (TSTR)
The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–4. TSTR is initialized to H'E0 or H'60 by a reset and in standby
mode.
Bit
7
6
5
4
3
2
1
0
—
—
—
STR4 STR3 STR2 STR1 STR0
Initial value
*
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W R/W R/W R/W R/W
Note: * Undefined
Bits 7–5—Reserved: Cannot be modified. Bit 7 is read as undefined. Bits 6 and 5 are always read
as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be
1.
Bit 4—Count Start 4 (STR4): STR4 starts and stops TCNT4.
Bit 4: STR4
0
1
Description
TCNT4 is halted
TCNT4 is counting
(Initial value)
Rev. 7.00 Jan 31, 2006 page 234 of 658
REJ09B0272-0700