SH7032 Datasheet, PDF (192/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
External
space
write
CK
A21–
A0
CSn
WR
External space writing
On-chip peripheral module read/write
T1
T2
T3
T4
T5
External space address
AD15–
AD0
Internal address
External space
address
Write data
On-chip supporting module address
On-chip
supporting
module
write
Internal
write
strobe
Internal
data bus
On-chip
supporting
module
read
Internal
read
strobe
Internal
data bus
Write data
Read data
Figure 8.34 Warp Mode Timing (Access to On-Chip Supporting Module and External
Write Cycle)
8.9 Wait State Control
The WCR1–WCR3 registers of the BSC can be set to control sampling of the WAIT signal when
accessing various areas, and the number of bus cycle states. Table 8.12 shows the number of bus
cycle states when accessing various areas.
Rev. 7.00 Jan 31, 2006 page 166 of 658
REJ09B0272-0700