SH7032 Datasheet, PDF (200/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
CK
RES
A0–A21
RAS
CAS
RD
RES latch
Tp
timing
Tr
Tc1
Tc2
Manual reset
Row address Column address FFFF
Figure 8.40 Long-Pitch Mode Read (1)
RES latch
timing
CK
Tp
Tr
Tc1
Tc2
RES
A0–A21
RAS
CAS
RD
Manual reset
Row address FFFF
Figure 8.41 Long-Pitch Mode Read (2)
For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM
data must be held after a reset, take one of the measures described below.
1. When resetting manually, use the watchdog timer (WDT) reset function.
2. Even if the low width of RAS becomes as short as 1.5 tcyc as shown above, use with a
frequency that satisfies the DRAM standard (t_RAS).
3. Even if the low width of RAS is 1.5 tcyc, use an external circuit so that a RAS signal with a
low width of 2.5 tcyc is input in the DRAM (if the low width of RAS is higher than 2.5 tcyc,
operate so that the current waveform is input in the DRAM).
These measures are not required when DRAM data is initialized or loaded again after a manual
reset.
Rev. 7.00 Jan 31, 2006 page 174 of 658
REJ09B0272-0700