SH7032 Datasheet, PDF (354/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
CK
TCNT
N
N+1
GRA
N
Compare
match A
signal
NDRB
n
PBDR
m
n
TP15–TP8
m
n
Figure 11.3 Transfer and Output Timing for NDRB Data (Example)
11.3.3 Examples of Use of Ordinary TPC Output
Settings for Ordinary TPC Output (Figure 11.4):
1. Select GRA as the output compare register (output disable) with the timer I/O control register
(TIOR).
2. Set the TPC output trigger cycle.
3. Select the counter clock with the TPSC2–TPSC0 bits in the timer control register (TCR).
Select the counter clear sources with the CCLR1 and CCLR0 bits.
4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to NDR can
also be set using the DMAC.
5. Set the initial output value in the I/O port data register to be used by the TPC.
6. Set the I/O port control register to be used by the TPC as the TP pin function (11).
7. Set to 1 the bit that performs TPC output to the next data enable register (NDER).
8. Select the ITU compare match that will be the TPC output trigger using the TPC output control
register (TPCR).
9. Set the next TPC output value in NDR.
10. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter.
11. Set the next output value in NDR whenever an IMIA interrupt is generated.
Rev. 7.00 Jan 31, 2006 page 328 of 658
REJ09B0272-0700