SH7032 Datasheet, PDF (177/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
Regardless of the state of the WAIT signal, when the RW1 bit, the number of wait states selected
by CBR refresh wait state insertion bits 1 and 0 (RLW1, RLW0) in the refresh control register
(RCR) are inserted into the CAS-before-RAS refresh cycle.
8.5.4 Byte Access Control
16-bit width and 18-bit width DRAMs require different types of byte control signals for access. By
setting the dual CAS signals/dual WE signals select bit (CW2) in DCR, the BSC allows selection
of either the dual CAS signal or dual WE signal system of control signals. When 16-bit space is
being accessed and the CW2 bit is cleared to 0 for dual CAS signals, CASH, CASL, and WRL
signals are output; when CW2 is set to 1 for dual WE signals, the CASL, WRH, and WRL signals
are output. When accessing 8-bit space, WRL and CASL are output regardless of the CW2 setting.
Figure 8.21 shows the control timing of the upper byte write cycle (short pitch) in 16-bit space.
Rev. 7.00 Jan 31, 2006 page 151 of 658
REJ09B0272-0700