SH7032 Datasheet, PDF (104/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Interrupt Controller (INTC)
Program
execution state
No
Interrupt?
Yes
NMI?
No
Yes
User break?
No
IRQOUT low^*1
Push SR onto stack
Push PC onto stack
Copy level of accep-
tance from I3 to I0
IRQOUT high^*2
Read exception
vector table
Branch to exception
handling routine
Yes
Yes
Level 15
No
interrupt?
Yes
I3 to I0 ≤
level 14?
No Yes
Level 14
interrupt?
Yes
I3 to I0 ≤
level 13?
No
Level 1 ^No
interrupt?
Yes
No Yes
I3 to I0 =
level 0?
No
I3 to I0: Interrupt mask bits of status register
Notes: 1. IRQOUT is the same signal as the interrupt request signal to the CPU (figure 5.1). The
IRQOUT pin returns to the high level when the interrupt controller has accepted the
interrupt of a level higher than that specified by bits I3 to I0 in the CPU's status register.
2. If the accepted interrupt is edge-sensed, the IRQOUT pin returns to the high level when
the instruction to be executed by the CPU is replaced by interrupt exception handling
(before the status register is saved to the stack ). If the interrupt controller has accepted
another interrupt of a level higher than the current interrupt, and has sent an interrupt
request to the CPU, however, the IRQOUT pin remains low.
Figure 5.2 Flowchart of Interrupt Operation
Rev. 7.00 Jan 31, 2006 page 78 of 658
REJ09B0272-0700