SH7032 Datasheet, PDF (291/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
• Input capture timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
CK
Input capture
input
Input capture
signal
TCNT
N
GRA/GRB
N
Figure 10.25 Input Capture Signal Timing
Rev. 7.00 Jan 31, 2006 page 265 of 658
REJ09B0272-0700