SH7032 Datasheet, PDF (145/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
Bits 9 and 8—Multiplex Shift Count 1 and 0 (MXC1 and MXC0): Shift row addresses
downward by a certain number of bits (8–10) when row and column addresses are multiplexed
(MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses
compared in burst operation.
Bit 9:
MXC1
0
1
Bit 8:
MXC0
0
1
0
1
Row Address Shift
(MXE = 1)
8 bits
(Initial value)
9 bits
10 bits
Reserved
Row Address Bits Compared
(in Burst Operation) (MXE = 0 or 1)
A8–A27
(Initial value)
A9–A27
A10–A27
Reserved
Bits 7–0—Reserved: These bits are always read as 0. The write value should always be 0.
8.2.6 Refresh Control Register (RCR)
The refresh control register (RCR) is a 16-bit read/write register that controls the start of refresh-
ing and selects the refresh mode and the number of wait states during refreshing. It is initialized to
H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
To prevent RCR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'5A is written in the upper byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
RFSHE RMODE RLW1 RLW0
—
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
—
—
—
—
Bit 15–8—Reserved: These bits are always read as 0.
Rev. 7.00 Jan 31, 2006 page 119 of 658
REJ09B0272-0700