SH7032 Datasheet, PDF (610/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.16 Timer Interrupt Enable Registers 0–4 (TIER0–TIER4)
ITU
Start Address: H'5FFFF06 (channel 0), H'5FFFF10 (channel 1), H'5FFFF1A (channel 2),
H'5FFFF24 (channel 3), H'5FFFF34 (channel 4),
Bus Width: 8
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE IMIEB IMIEA
Initial value
*
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: * Undetermined
Table A.17 TIER0–TIER4 Bit Functions
Bit Bit name
2 Overflow interrupt enable (OVIE)
1 Input capture/compare match
interrupt enable B (IMIEB)
0 Input capture/compare match
interrupt enable A (IMIEA)
Value
0
1
0
1
0
1
Description
Interrupt request by OVF (OVI) disabled
(Initial value)
Interrupt request by OVF (OVI) enabled
Interrupt request by IMFB (IMIB) disabled
(Initial value)
Interrupt request by IMFB (IMIB) enabled
Interrupt request by IMFA (IMIA) disabled
(Initial value)
Interrupt request by IMFA (IMIA) enabled
Rev. 7.00 Jan 31, 2006 page 584 of 658
REJ09B0272-0700